Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 39
Clock Stop
T0
T1
T2
Tn
CK
CK
CKE
Timing Condition
NOP NOP
NOP
Exit
CMD
Valid
NOP
Command
= Don't Care
Clock
Stopped
Enter
Clock
Stop
Clock Command
Stop
TABLE 16
Minimum Number of Required Clock Pulses per Access Command
Command
Timing Condition
- 6
- 7.5
Unit
tCK
Note
1)
ACTIVE
tRCD
3
5
5
6
9
3
3
5
5
5
8
3
1)2)
1)2)3)
1)2)
1)2)
1)
READ (Auto-Precharge Disabled)
READ (Auto-Precharge Enabled)
WRITE (Auto-Precharge Disabled)
WRITE (Auto-Precharge Enabled)
PRECHARGE
(BL / 2) + CL
tCK
tCK
tCK
tCK
tCK
tCK
tCK
[(BL / 2) + tRP]; [(BL / 2) + CL]
1 + (BL / 2) + tWR
1 + (BL / 2) + tDAL
tRP
1)
AUTO REFRESH
tRFC
tMRD
12
2
10
2
MODE REGISTER SET
1) These parameters depend on the operating frequency; the number of clock cycles shown are calculated for a clock frequency of 133 MHz
for -7.5.
2) The values apply for a burst length of 4 and a CAS latency of 3.
3) Both timing conditions need to be satisfied; if not equal, the larger value applies
2.4.12
Clock Frequency Change
Depending on system considerations, it might be desired to change the DDR Mobile-RAM’s clock frequency while the device
is powered up. The DDR Mobile-RAM supports a clock frequency change when the device is in:
•
•
•
self refresh mode (see Figure 36);
power-down mode (see Figure 38);
clock stop mode (see Figure 39).
Once the clock runs stable at the new clock frequency, the timing conditions for exiting these states have to be met before
applying the next access command. It should be pointed out that a continuous frequency drift is not considered a stable clock
and therefore is not supported.
Rev.1.0, 2007-03
47
10242006-Y557-TZXW
QIMONDA [ QIMONDA AG ]
