HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
3.2
AC Characteristics
Table 20
AC Characteristics1)2)3)4)
Parameter
Symbol
tCK
- 7.5
Unit Notes
min.
7.5
9.5
—
max.
—
Clock cycle time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
ns
ns
—
—
Clock frequency
fCK
133
105
5.4
6.0
—
MHz
MHz
ns
—
—
5)6)
Access time from CLK
tAC
—
—
ns
Clock high-level width
tCH
tCL
tIS
2.5
2.5
1.5
0.5
0.8
2
ns
—
Clock low-level width
—
ns
—
7)
Address, data and command input setup time
Address and command input hold time
Data (DQ) input hold time
—
ns
7)
tIH
—
ns
—
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
tMRD
tLZ
—
tCK
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ms
tCK
—
—
1.0
3.0
2.5
—
–
tHZ
7.0
—
—
5)6)
tOH
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
tDQZ
tDQW
tRC
2
—
0
—
—
8)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
67
19
15
45
14
19
—
—
8)
8)
8)
9)
8)
tRCD
tRRD
tRAS
tWR
—
—
100k
—
PRECHARGE command period
Refresh period (8192 rows)
tRP
—
tREF
tSREX
64
—
—
—
Self refresh exit time
1
1) 0 °C ≤ TC ≤ 70 °C (comm.), -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.70V to 1.95V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time tT is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
5) Specified tAC and tOH parameters are measured with a 30 pF capacitive load only as shown below:
I/O
30 pF
6) If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter.
7) If tT > 1 ns, a value of [0.5 x (tT - 1)] ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ≤ 72 MHz.
With fCK > 72 MHz two clock cycles for tWR are mandatory. Qimonda recommends to use two clock cycles for the write
recovery time in all applications.
Data Sheet
42
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
