Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
3
Functional Description
This chapter list all defined commands and their usage for this Synchronous DRAM family.
TABLE 5
Truth Table: Operation Command
Operation
Device State
CKE
CKE
n1)2)
DQM BA0
AP=
Addr. CS1 RAS CAS1 WE
1)2)
1)2)
)2)
1)2)
)2)
1)2)
n-11)2)
BA11)2) A101)2)
Bank Active
Bank Precharge
Precharge All
Write
Idle3)
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
L
V
X
X
V
V
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
Any
L
Any
H
L
L
Active3)
Active3)
H
H
Write with Auto
precharge
H
L
Read
Active3)
Active3)
H
H
X
X
X
X
V
V
L
V
V
L
L
H
H
L
L
H
H
Read with Auto
precharge
H
Mode Register Set
No Operation
Idle
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
L
L
L
L
L
Any
H
H
X
L
H
H
X
L
H
L
Burst Stop
Active
L
Device Deselect
Auto Refresh
Any
H
L
X
H
H
X
X
X
H
X
H
X
Idle
Self Refresh Entry
Self Refresh Exit
Idle
L
L
L
Idle (Self Refr.)
H
H
L
X
H
X
H
X
H
X
X
H
X
H
X
H
X
Power Down/
Clock Suspend Entry or Burst
Active or Idle
H
L
L
X
X
X
X
X
X
X
X
H
L
Power Down/
Clock Suspend Exit
Active or Idle
or Burst
H
H
L
Data Write/
Output Enable
Active
H
H
X
X
L
X
X
X
X
X
X
X
Data Write/
Active
H
X
X
X
X
Output Disable
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
3) This is the state of the banks designated by BA0, BA1 signals.
Rev. 1.32, 2007-10
9
10122006-I6LJ-WV3H
QIMONDA [ QIMONDA AG ]
