Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
1
Overview
This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information.
1.1
Features
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Double data rate architecture: two data transfers per clock
cycle
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
DQS is edge-aligned with data for reads and is center-
aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
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Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
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V
V
V
V
DDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333);
DDQ = 2.6 V ± 0.1 V (DDR400)
DD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333);
DD = 2.6 V ± 0.1 V (DDR400)
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Standard Temperature Range (0 °C - +70 °C) or Industrial
Temperature Range (–40 °C - +85 °C)
P-TFBGA-60-12 package with 3 depopulated rows
(8 × 12 mm2)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
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P-TSOPII-66 package
CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
RoHS1) compliant product types available (green product)
TABLE 1
Performance of –5, –6 and –7
Product Type Speed Code
–5
–6
–7
Unit
Speed Grade Component
DDR400B
200
DDR333B
166
DDR266A
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—
Max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 2.3, 2007-03
3
03062006-8CCM-VPUW