Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Symbol
Values
Typ.
Unit
Note/
Test Condition
Min.
Max.
Input Capacitance: CK, CK
CI1
1.5
2.0
—
—
—
—
—
—
—
2.5
3.0
0.25
2.5
3.0
0.5
pF
pF
pF
pF
pF
pF
P-TFBGA-60-121)
P-TSOPII-66 1)
1)
Delta Input Capacitance
CdI1
CI2
Input Capacitance: All other input-only pins
1.5
2.0
—
P-TFBGA-60-12 1)
P-TSOPII-66 1)
1)
Delta Input Capacitance: All other input-only CdIO
pins
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
—
4.5
pF
P-TFBGA-60-12
P-TFBGA-60-12 1)2)
4.0
—
—
—
5.0
0.5
pF
pF
P-TSOPII-66 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS,
DM
CdIO
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only. VDDQ = VDD
2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
=
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 2.3, 2007-03
23
03062006-8CCM-VPUW