Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
1.2
Description
The 256 Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank
DRAM.
DQS, as well as to both edges of CK. Read and write
accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits
registered coincident with the Active command are used to
select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are
used to select the bank and the starting column location for
the burst access.
The 256 Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
256 Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with SSTL_2. All
outputs are SSTL_2, Class II compatible.
The 256 Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
Rev. 2.3, 2007-03
4
03062006-8CCM-VPUW
QIMONDA [ QIMONDA AG ]
