Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
%$ꢄ %$ꢁ $ꢄꢃ $ꢄꢄ $ꢄꢁ
$ꢊ
$ꢉ
$ꢂ
$ꢈ
$ꢇ
&/
$ꢆ
$ꢅ
%7
$ꢃ
$ꢄ
%/
$ꢁ
ꢁ
ꢁ
23(5$7,1*ꢀ02'(
03%'ꢃꢁꢊꢁ
TABLE 7
Mode Register
Field
Bits
Type1) Description
Burst Length
BL
[2:0]
W
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
See Table 8 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
110B 2.5
101B 1.5
Note: DDR200 components only
Operating Mode
MODE [12:7]
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 2.3, 2007-03
14
03062006-8CCM-VPUW
QIMONDA [ QIMONDA AG ]
