Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
%
$
ꢁꢀ
%
$
ꢂꢀ
ꢂꢀ
Uꢀ
$
ꢁ
ꢃꢀ
$
ꢁ
ꢁꢀ
$
ꢁ
ꢂꢀ
UD LQ
Zꢀ
$
ꢄꢀ
$
ꢅꢀ
$
ꢆꢀ
$
ꢇꢀ
$
ꢈꢀ
&/
Zꢀ
$
ꢉꢀ
$
ꢊꢀ
7ꢀ
$ꢃꢀ
$
%
ꢁꢀ
/ꢀ
$ꢂꢀ
ꢀ
%
ꢂꢀ
UH
2S
H
W
Jꢀ0
2'
(ꢀ
JꢋꢀD
G
G
Zꢀ
Zꢀ
TABLE 7
Mode Register Definition
Field Bits
Type Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
w
w
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
101B (1.5 Optional, not covered by this data sheet)
110B 2.5
MODE [12:7]
w
Operating Mode
Note: All other bit combinations are RESERVED.
000000B Normal Operation without DLL Reset
000010B DLL Reset
Rev. 1.63, 2006-09
14
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
