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HYB25DC128800C 参数 Datasheet PDF下载

HYB25DC128800C图片预览
型号: HYB25DC128800C
PDF下载: 下载PDF文件 查看货源
内容描述: 128 - Mbit的双数据速率SDRAM [128-Mbit Double-Data-Rate SDRAM]
分类和应用: 动态存储器
文件页数/大小: 32 页 / 1836 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB25DC128[800/160]C[E/F]  
128-Mbit Double-Data-Rate SDRAM  
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a  
strobe transmitted by the during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads  
and center-aligned with data for Writes.  
The 128-Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and  
CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every  
positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as  
well as to both edges of CK.  
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a  
programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command,  
which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used  
to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used  
to select the bank and the starting column location for the burst access.  
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function  
may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.  
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby  
providing high effective bandwidth by hiding row precharge and activation time.  
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the Industry  
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.  
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of  
operation.  
TABLE 2  
Order Information for RoHS Compliant Products  
Part Number1)  
Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed  
Package  
Note  
Latencies  
(MHz) Latencies  
(MHz)  
2)  
HYB25DC128800CE-5  
HYB25DC128160CE-5  
HYB25DC128160CF-5  
×8  
3-3-3  
200  
2.5-3-3  
166  
DDR400B PG-TSOPII-66  
×16  
×16  
PG-TFBGA-60  
HYB25DC128800CE–6 ×8  
HYB25DC128160CE–6 ×16  
HYB25DC128800CF–6 ×8  
HYB25DC128160CF–6 ×16  
2.5-3-3  
166  
2-3-3  
133  
DDR333B PG-TSOPII-66  
PG-TFBGA-60  
1) HYB: designator for memory components  
25DC: s at VDDQ = 2.5 V  
128: 128-Mbit density  
800/160: Product variations ×8 and ×16  
C: Die revision C  
F/E: Package type TSOP and FBGA  
L: Low power version (available on request) - these components are specifically selected for low IDD6 Self Refresh currents  
-5, - 6: speed grade  
2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.1, 2007-01  
4
03062006-JXUK-E7R1