Internet Data Sheet
HYB25DC128[800/160]C[E/F]
128-Mbit Double-Data-Rate SDRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 15
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
DDQ + 0.5
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
—
—
—
—
—
—
1
V
V
+3.6
+3.6
+3.6
+70
+150
—
V
VDD
V
VDDQ
TA
V
°C
°C
W
mA
TSTG
PD
–55
—
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
—
50
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
TABLE 16
Input and Output Capacitances
Parameter
Symbol
Values
Unit Note/ Test Condition
Min. Typ. Max.
Input Capacitance: CK, CK
CI1
2.0
1.5
—
—
—
—
—
—
—
—
—
—
3.0
2.5
pF
pF
TSOPII 1)
TFBGA 1)
1)
Delta Input Capacitance
CdI1
CI2
0.25 pF
Input Capacitance: All other input-only pins
1.5
2.0
—
2.5
3.0
0.5
4.5
5.0
0.5
pF
pF
pF
pF
pF
pF
TFBGA 1)
TSOPII 1)
1)
Delta Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ, DQS, DM
CdIO
CIO
3.5
4.0
—
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 1.1, 2007-01
18
03062006-JXUK-E7R1
QIMONDA [ QIMONDA AG ]
