Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
Values
Typ.
Unit
Note/
Test Condition
Min.
Max.
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
4.0
—
—
—
—
4.5
5.0
0.5
pF
pF
pF
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS,
DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
TABLE 17
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note1)/Test Condition
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
VDD
2.3
2.5
2.3
2.5
0
2.5
2.6
2.5
2.6
—
2.7
2.7
2.7
2.7
0
V
V
V
V
V
fCK ≤ 166 MHz
f
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
VDD
VDDQ
VDDQ
fCK > 166 MHz 2)3)
Supply Voltage, I/O Supply VSS, VSSQ
Voltage
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
V
I/O Termination Voltage
(System)
VREF – 0.04
—
VREF + 0.04
6)
6)
6)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
VREF + 0.15
–0.3
—
—
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
V
V
Input Voltage Level, CK and VIN(DC)
–0.3
CK Inputs
6)7)
8)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
0.71
–2
—
—
—
—
—
—
VDDQ + 0.6
V
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
µA
µA
Input Leakage Current
Output Leakage Current
II
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V9)
IOZ
–5
5
DQs are disabled; 0 V ≤ VOUT
VDDQ
≤
9)
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA VOUT
=
1.95 V
Output Low Current, Normal IOL
16.2
mA VOUT = 0.35 V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V;
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ
.
.
Rev. 1.3, 2006-12
21
03292006-W2FE-ELDX
QIMONDA [ QIMONDA AG ]
