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HYB25D512800BT-5 参数 Datasheet PDF下载

HYB25D512800BT-5图片预览
型号: HYB25D512800BT-5
PDF下载: 下载PDF文件 查看货源
内容描述: 512 - Mbit的双数据速率SDRAM [512-Mbit Double-Data-Rate SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 38 页 / 2063 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB25D512[40/16/80]0B[E/F/C/T](L)  
Double-Data-Rate SDRAM  
TABLE 21  
IDD Conditions  
Parameter  
Symbol  
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN  
;
IDD0  
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two  
clock cycles.  
Operating Current: one bank; active/read/precharge; Burst = 4;  
IDD1  
Refer to the following page for detailed test conditions.  
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK = tCKMIN  
IDD2P  
IDD2F  
Precharge Floating Standby Current: CS VIHMIN, all banks idle;  
CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS  
and DM.  
Precharge Quiet Standby Current:  
IDD2Q  
CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable  
at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM.  
Active Power-Down Standby Current: one bank active; power-down mode;  
CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.  
IDD3P  
Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N  
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.  
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing  
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,  
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA  
IDD4R  
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing  
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,  
CL = 3 for DDR333; tCK = tCKMIN  
IDD4W  
Auto-Refresh Current: tRC = tRFCMIN, burst refresh  
IDD5  
IDD6  
IDD7  
Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN  
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test  
conditions.  
Rev. 1.63, 2006-09  
31  
03062006-PFFJ-YJY2  
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