Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics
1.1
Features
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Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: (1.5), 2, 2.5, 3
Auto Pre charge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP=tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
V
DDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
DD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
P-TFBGA-60 and P-TSOPII-66 package
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade Component
Module
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
DDR266A
—
PC2100–2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
–
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
Rev. 1.63, 2006-09
3
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
