Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM
is internally configured as a quad-bank DRAM.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row).
The address bits registered coincident with the Read or Write
command are used to select the starting column location for
the burst access.
The 512-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double-data-rate architecture is essentially a 2n pre fetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM consists
of a single 2n-bit wide, one clock cycle data transfer at the
internal DRAM core and two corresponding n-bit wide, one-
half clock cycle data transfers at the I/O pins.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Rev. 1.63, 2006-09
13
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
