Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter contains features and the description.
1.1
Features
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Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
V
DDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
DD = 2.5 V ± 0.2 V (DDR266A, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
P(G)-TFBGA-60 package with 3 depopulated rows (8 × 12 mm2)
P(G)-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade
Component
Module
@CL3
DDR400B
PC3200-3033
200
DDR333
PC2700–2533
166
DDR266A
—
PC2100-2033
—
max. Clock Frequency
fCK3
—
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5 166
fCK2 133
166
143
133
133
Rev. 1.6, 2007-02
3
03292006-U5AN-6TI1