Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 7
Input/Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE Low provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are
disabled during power-down. Input buffers, excluding CKE, are disabled during self
refresh. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is
applied on first power up. After VREF has become stable during the power on and
initialization sequence, it must be mantained for proper operation of the CKE receiver.
For proper self-refresh entry and exit, VREF must be mantained to this input.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple banks. CS is considered part of the
command code. The standard pinout includes one CS pin.
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading.
BA0, BA1
A0 - A12
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
DQ
Input/Output
Input/Output
Data Input/Output: Data bus.
DQS
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
N.C.
VDDQ
VSSQ
VDD
–
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
DQ Ground
Supply
Supply
Supply
Supply
Supply
Power Supply: 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
Ground
VSS
VREF
SSTL_2 Reference Voltage: (VDDQ/2)
Rev. 1.70, 2007-11
14
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
