Internet Data Sheet
HYB25D512[400/160/800]C[E/T/F/C](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 22
IDD Specification for HYB25D512[400/160/800]C[EF](L)
–6
–5
Unit
Note1)
DDR333
Typ.
DDR400B
Typ.
Symbol
Max.
Max.
IDD0
60
70
60
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×4/×8 2)3)
×16 3)
×4/×8 3)
×16 3)
3)
70
85
75
90
IDD1
65
80
70
85
80
95
90
110
4.6
30
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
1.1
21
4.6
25
1.1
25
3)
3)
3)
15
22
17
23
11
15
12
16
32
37
35
42
×4/×83)
×16 3)
×4/×8 3)
×16 3)
×4/×8 3)
×16 3)
33
40
38
45
IDD4R
70
85
80
90
95
115
90
110
85
135
95
IDD4W
75
100
130
1.6
—
120
175
5
115
145
1.6
—
135
190
5
3)
IDD5
IDD6
4)
2.5
205
230
2.5
230
250
low power part(L)
×4/×83)
×16 3)
IDD7
175
190
195
210
1) Test conditions for typical values: VDD = 2.5 V (DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum values:
VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 166 MHz for DDR333, and 200 MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.31, 2006-09
31
03292006-3TFJ-HNV3
QIMONDA [ QIMONDA AG ]
