Internet Data Sheet
HYB25D512[400/160/800]C[E/T/F/C](L)
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
Features
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Double data rate architecture: two data transfers per clock
cycle
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
DQS is edge-aligned with data for reads and is center-
aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
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Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP=tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V
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VDD = 2.5 V ± 0.2 V
P-TFBGA-60-11 package
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
P-TSOPII-66-1 package
RoHS Compliant Products1)
TABLE 1
Performance for –5 and –6
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
@CL3
DDR400B
200
DDR333B
166
—
Max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.31, 2006-09
3
03292006-3TFJ-HNV3
QIMONDA [ QIMONDA AG ]
