Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
3
Functional Description
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TABLE 7
MR Mode Register Definition (BA[1:0] = 00B)
Field
BL
Bits Type1) Description
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
w
w
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
101B 1.5
Note: DDR200 components only
110B 2.5
MODE [11:7] w
Operating Mode
Note: All other bit combinations are RESERVED.
00000B
00010B
Normal Operation without DLL Reset
Normal Operation with DLL Reset
1) w=write
Rev. 1.6, 2007-02
12
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
