Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
TABLE 23
AC Timing - Absolute Specifications
Parameter
Symbol –7
DDR266A
Min.
Unit Note1)/ Test
Condition
Max.
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
tAC
tCH
tCK
–0.75
+0.75
0.55
12
ns
tCK
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
ns
ns
tCK
ns
tCK
tCK
ns
ns
ns
0.45
—
Clock cycle time
7.5
CL = 3.0
CL = 2.5
CL = 2.0
7.5
12
7.5
12
CK low-level width
tCL
0.45
0.55
—
6)
Auto precharge write recovery + precharge time
DQ and DM input hold time
tDAL
tDH
(tWR/tCK)+(tRP/tCK)
0.5
—
—
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (DQS and associated DQ signals)
DQS-DQ skew (DQS and associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time
tDIPW
tDQSCK
tDQSL,H
tDQSQ
tDQSQ
tDQSS
tDS
1.75
–0.75
0.35
—
—
—
+0.75
—
—
—
+0.5
+0.5
1.25
—
TFBGA
TSOPII
—
—
0.75
0.5
—
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock Half Period
tDSH
tDSS
tHP
0.2
—
—
0.2
—
—
min. (tCL, tCH
)
—
—
7)
Data-out high-impedance time from CK/CK
Address and control input hold time
tHZ
—
+0.75
—
tIH
0.9
fast slew rate
8)
1.0
1.1
ns
slow slew rate
9)
Control and Addr. input pulse width (each input)
Address and control input setup time
tIPW
tIS
2.2
0.9
—
—
ns
ns
fast slew rate
1.0
—
ns
slow slew rate
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
tLZ
–0.75
2
+0.75
—
ns
tCK
ns
—
—
—
tMRD
tQH
t
HP –tQHS
—
Rev. 1.6, 2007-02
28
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
