Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 12
Truth Table 2: Clock Enable (CKE)
Current State CKE n-1
CKEn
Command n
Action n
Note
Previous
Cycle
Current
Cycle
1)
2)
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
—
L
L
X
Maintain Self-Refresh
Exit Self-Refresh
L
H
L
Deselect or NOP
X
L
Maintain Power-Down
Exit Power-Down
—
—
—
—
—
—
L
H
L
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See Table 13
H
H
H
H
Precharge Power-Down Entry
Self Refresh Entry
Active Power-Down Entry
—
L
L
H
1)
VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 1.6, 2007-02
16
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
