Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Ball No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
185
186
52
CK0
CK0
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
—
Clock Signal CK0, Complementary Clock Signal CK0
I
I
Clock Enables 1:0
Note: 2-Ranks module
171
I
NC
Not Connected
Note: 1-Rank module
Control Signals
193
76
S0
S1
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2-Ranks module
I
NC
Not Connected
Note: 1-Rank module
192
RAS
I
I
I
I
SSTL
SSTL
SSTL
CMOS
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
74
CAS
73
WE
18
RESET
Register Reset
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.4, 2007-02
6
03062006-GD6J-14FP
QIMONDA [ QIMONDA AG ]
