Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
The 256-Mbit Double-Data-Rate-Two SDRAM is a high-
speed CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The device is organized as either 16 Mbit × 4 I/O ×
4 banks, 8 Mbit × 8 I/O × 4 banks or 4 Mbit ×16 I/O × 4 banks
chip. These synchronous devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications. See Table 1 for performance figures.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A
is used to convey row, column and bank address
information in a RAS-CAS multiplexing style.
The device is designed to comply with all DDR2 DRAM key
features:
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
•
•
•
•
•
Posted CAS with additive latency,
Write latency = read latency - 1,
Normal and weak strength data-output driver,
Off-Chip Driver (OCD) impedance adjustment
On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in P(G)-TFBGA-60 and P(G)-
TFBGA-84 packages.
Rev. 1.11, 2007-07
5
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
