Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.3
256-Mbit DDR2 Addressing
This chapter describes the 256-Mbit DDR2 addressing.
TABLE 15
DDR2 Addressing for ×4 Organization
Configuration
64Mb x 41)
Note
Bank Address
BA[1:0]
4
Number of Banks
Auto-Precharge
A10 / AP
A[12:0]
A11, A[9:0]
11
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
4
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
TABLE 16
DDR2 Addressing for ×8 Organization
Configuration
32Mb x 81)
Note
Bank Address
BA[1:0]
4
Number of Banks
Auto-Precharge
A10 / AP
A[12:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
8
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
TABLE 17
DDR2 Addressing for ×16 Organization
Configuration
16Mb x 161)
Note
Bank Address
Number of Banks
Auto-Precharge
Row Address
BA[1:0]
4
A10 / AP
A[12:0]
Rev. 1.11, 2007-07
19
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
