Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Chip Configuration for ×8 components, PG-TFBGA-60 (top view)
ꢅ
ꢈ
ꢆ
ꢃ
ꢁ
ꢂ
ꢇ
ꢊ
ꢉ
$
9''
966
9664
9''4
1&ꢄ5'46
'46
9664
9664
%
&
'
(
)
*
+
-
'4ꢂ
'0ꢄ5'46
'46
'4ꢇ
9''4
9''4
9''4
9''4
'4ꢅ
'4ꢀ
9664
9664
'4ꢃ
'4ꢆ
'4ꢈ
966'/
5$6
&$6
$ꢈ
'4ꢁ
9''/
95()
966
9''
&.
&.
&.(
%$ꢀ
$ꢅꢀꢄ$3
$ꢆ
:(
%$ꢅ
$ꢅ
2'7
1&
&6
9''
$ꢀ
966
$ꢁ
$ꢂ
$ꢃ
966
.
/
$ꢇ
$ꢉ
$ꢅꢅ
1&
$ꢊ
9''
$ꢅꢈ
1&
1&ꢋꢌ$ꢅꢆ
0337ꢀꢁꢂꢀ
Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
Rev. 1.11, 2007-07
14
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
