Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
2
Chip Configuration
This chapter contains the chip configuration and addressing.
2.1
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in Figure 1
for ×4, Figure 2 for ×8 and Figure 3 for ×16.
TABLE 7
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4/×8 organization
E8
F8
F2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
CK
CKE
Clock Signals ×16 organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
K8
K2
CK
CKE
Clock Enable
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
F7
G7
F3
G8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Control Signals ×16 organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×4/×8 organizations
G2
G3
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 1:0
Rev. 1.1, 2007-05
8
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
