HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration for ×4 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration for ×8 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration for ×16 components, PG-TFBGA-84-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Single-ended AC Input Test Conditions Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . 31
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins. . . . . . . . . . . . . . . . 32
Package Pinout PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Internet Data Sheet
54
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
