Internet Data Sheet
HYB18TC512[80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)7)
Operating Bank Interleave Read Current
IDD7
All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD)
,
t
RC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs
are stable during deselects; Data pattern is same as IDD4R;
Refer to the following pages for detailed timing conditions
1)
2)
3)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized.
DD parameter are specified with ODT disabled.
I
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) For IDD definition see Table 39
6) Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
7) A - Activate, RA - Read with Auto-Precharge, D - Deselect
TABLE 39
Definition for IDD
Parameter
Description
LOW
Defined as VIN ≤ VIL(AC).MAX
HIGH
Defined as VIN ≥ VIH(AC).MIN
STABLE
FLOATING
SWITCHING
Defined as inputs are stable at a HIGH or LOW level
Defined as inputs are VREF = VDDQ / 2
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Rev. 1.21, 2007-09
32
03292006-HDLH-OAY6
QIMONDA [ QIMONDA AG ]
