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HYB18TC256160BF-2.5 参数 Datasheet PDF下载

HYB18TC256160BF-2.5图片预览
型号: HYB18TC256160BF-2.5
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆位双数据速率 - 双SDRAM的 [256-Mbit Double-Data-Rate-Two SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 62 页 / 3539 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC256[80/16]0BF  
256-Mbit Double-Data-Rate-Two SDRAM  
1
Overview  
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main  
characteristics.  
1.1  
Features  
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:  
1.8 V ± 0.1 V Power Supply  
Off-Chip-Driver impedance adjustment (OCD) and On-  
Die-Termination (ODT) for better signal quality  
Auto-Precharge operation for read and write bursts  
Auto-Refresh, Self-Refresh and power saving Power-  
Down modes  
Average Refresh Period 7.8 µs at a TCASE lower than  
85 °C, 3.9 µs between 85 °C and 95 °C  
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
Full and reduced Strength Data-Output Drivers  
1K page size  
Packages: PG-TFBGA-84, PG-TFBGA-60  
RoHS Compliant Products1)  
All Speed grades faster than DDR400 comply with  
DDR400 timing specifications when run at a clock rate of  
200 MHz  
1.8 V ± 0.1 V (SSTL_18) compatible I/O  
DRAM organizations with 8 and 16 data in/outputs  
Double Data Rate architecture: two data transfers per  
clock cycle four internal banks for concurrent operation  
Programmable CAS Latency: 3, 4, 5 and 6  
Programmable Burst Length: 4 and 8  
Differential clock inputs (CK and CK)  
Bi-directional, differential data strobes (DQS and DQS) are  
transmitted / received with data. Edge aligned with read  
data and center-aligned with write data.  
DLL aligns DQ and DQS transitions with clock  
DQS can be disabled for single-ended data strobe  
operation  
Commands entered on each positive clock edge, data and  
data mask are referenced to both edges of DQS  
Data masks (DM) for write data  
Posted CAS by programmable additive latency for better  
command and data bus efficiency  
TABLE 1  
Performance tables for –2.5  
Product Type Speed Code  
Speed Grade  
–2.5  
Unit  
DDR2–800E 6–6–6  
Max. Clock Frequency  
@CL6  
@CL5  
@CL4  
@CL3  
fCK6  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
400  
333  
266  
200  
15  
MHz  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
45  
ns  
60  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.3, 2007-05  
3
07182006-DD60-22E6