Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
J2
J1
J7
VREF
VDDL
VSSDL
Al
—
—
—
I/O Reference Voltage
Power Supply
PWR
PWR
Power Supply
Not Connected ×8 Organization
A1, A2, A8, A9, NC
R7, W1, W2,
NC
—
Not Connected
W8, W9, R3
Other Balls ×8 Organizations
K9
ODT
I
SSTL
On-Die Termination Control
TABLE 7
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 8
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.21, 2007-07
9
02282007-F8UP-4HSU