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HYB18TC1G160BF-2.5 参数 Datasheet PDF下载

HYB18TC1G160BF-2.5图片预览
型号: HYB18TC1G160BF-2.5
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 65 页 / 3555 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0BF  
1-Gbit Double-Data-Rate-Two SDRAM  
2
Configuration  
This chapter contains the chip configuration and addressing.  
2.1  
Chip Configuration for PG-TFBGA-68  
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# and Buffer Type  
columns are explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is depicted in figures.  
TABLE 6  
Chip Configuration of DDR2 SDRAM  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Clock Signals ×8 Organizations  
J8  
CK  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal CK, CK  
Clock Enable  
K8  
K2  
CK  
CKE  
Control Signals ×8 Organizations  
K7  
L7  
K3  
L8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
CS  
Chip Select  
Address Signals ×8 Organizations  
L2  
L3  
L1  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
Bank Address Bus 2  
Note: 1 Gbit components and higher  
Note: 256 Mbit and 512 Mbit components  
NC  
Rev. 1.21, 2007-07  
7
02282007-F8UP-4HSU