Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 37
Speed Grade Definition
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
DDR2–533C
DDR2–400B Unit Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
–5
4–4–4
5–5–5
4–4–4
Min.
3–3–3
Min.
tCK
Symbol Min.
Max.
Min.
Max.
Max.
Max.
—
1)2)3)4)
Clock Period @ CL = 3
@ CL = 4
tCK
5
8
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
tCK
3
8
3.75
3
8
3.75
3.75
45
8
5
8
1)2)3)4)
@ CL = 5
tCK
3
8
8
8
5
8
1)2)3)4)5)6)
1)2)3)4)5)7)
1)2)3)4)6)
1)2)3)4)7)
1)2)3)4)
Row Active Time
Row Active Time
Row Cycle Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRAS
tRC
45
40
57
52
12
12
70k
70k
—
—
—
—
45
40
60
55
15
15
70k
70k
—
—
—
—
70k
70k
—
—
—
—
40
40
55
55
15
15
70k
70k
—
—
—
—
40
60
tRC
55
tRCD
tRP
15
1)2)3)4)
15
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. CKDQS RDQS
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
6) For products released before 01-09-2007.
7) Products released after 01-09-2007 can support tRAS.MIN = 40 ns for all DDR2 speed sort.
Rev. 1.40, 2008-03
42
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
