Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Chip Configuration for ×4 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Configuration for ×8 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Configuration for ×16 components, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 37
Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Differential input waveform timing - tlS and tlH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Outline P(G)-TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package Outline P(G)-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Rev. 1.12, 2007-05
65
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
