Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
4 GByte
4 GByte
4 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×8)
Label Code
PC2– PC2– PC2– PC2–
5300R–555 4200R–444 3200R–333 3200R–333
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
t
t
t
CK.MAX [ns]
80
18
22
0F
50
58
37
21
21
24
23
17
4A
21
28
00
00
00
00
12
54
7F
7F
7F
7F
7F
80
1E
28
0F
50
00
00
00
00
00
00
00
00
00
00
00
00
00
00
12
D4
7F
7F
7F
7F
7F
80
23
2D
0F
50
00
00
00
00
00
00
00
00
00
00
00
00
00
00
12
4E
7F
7F
7F
7F
7F
80
23
2D
0F
51
60
33
1A
23
18
18
16
35
21
25
C4
8C
59
5C
12
EA
7F
7F
7F
7F
7F
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Rev. 1.2, 2007-01
33
03292006-AYVF-ZIIJ
QIMONDA [ QIMONDA AG ]
