Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration.
2.1
Configuration for TFBGA-60
The chip configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 5 and Table 6 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 4
Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals
E8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
F8
CK
F2
CKE
Control Signals
F7
G7
F3
G8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals
G2
G3
H8
H3
H7
J2
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
BA1
A0
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
J8
A4
J3
A5
J7
A6
K2
K8
K3
H2
A7
A8
A9
A10
AP
A11
A12
K7
L2
Rev. 1.50, 2007-12
8
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
