Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
–5
Unit
Note
DRAM Speed Grade
DDR2 –800D
–800E
6–6–6
–667C
4–4–4
–667D
5–5–5
–533C
4–4–4
–400B
3–3–3
CAS-RCD-RP latencies
5–5–5
tCK
Max.
Clock Frequency
CL3 fCK3
CL4 fCK4
200
200
266
333
400
15
200
333
333
–
200
266
333
–
200
266
266
–
200
200
–
MHz
MHz
MHz
MHz
ns
266
400
–
CL5 fCK5
CL6 fCK6
–
Min. RAS-CAS-Delay
tRCD
tRP
12.5
12.5
12
15
15
15
15
Min. Row Precharge
Time
15
12
15
15
ns
Min. Row Active Time
Min. Row Cycle Time
tRAS
tRC
45
45
60
15
45
57
12
45
60
15
45
60
15
40
55
15
ns
ns
ns
57.5
12.5
Precharge-All (4 banks) tPREA
command period
1.2
Description
The 256-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The 256-Mbit device is organized as 16 Mbit ×4 I/O ×4
banks or 8 Mbit ×8 I/O ×4 banks or 4 Mbit ×16 I/O ×4 banks
chip.
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15 bit address bus for ×4 and ×8 organised components
and a 15 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
A 15 bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.50, 2007-12
4
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
