Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration.
2.1
Configuration for FBGA-60
The chip configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Ball# and BufferType
column are explained in Table 5 and Table 6 respectively.
TABLE 4
Chip Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4 /×8 Organizations
E8
F8
F2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
CK
CKE
Control Signals ×4 /×8 Organizations
F7
G7
F3
G8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×4 /×8 Organizations
G2
G3
G1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Rev. 1.60, 2008-08
8
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
