Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 42
Absolute Jitter Value Definitions
Symbol Parameter
Min.
Max.
Unit
tCK.ABS
tCH.ABS
Clock period
t
t
CK.AVG(Min) + tJIT.PER(Min)
t
t
CK.AVG(Max) + tJIT.PER(Max)
CH.AVG(Max) x tCK.AVG(Max) +
ps
ps
Clock high-pulse width
CH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min)
tJIT.DUTY(Max)
tCL.ABS
Clock low-pulse width
tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max)
+
ps
tJIT.DUTY(Max)
Example: for DDR2-667, tCH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 43 shows clock-jitter specifications.
TABLE 43
Clock-Jitter Specifications for –667, –800 and –1066
Symbol
Parameter
DDR2 -667
DDR2 -800
DDR2-1066
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tCK.AVG
tJIT.PER
Average clock period nominal w/o
jitter
3000
8000
2500
8000
TBD
TBD
ps
Clock-period jitter
–125
+125
+100
–100
–80
+100
+80
TBD
TBD
TBD
TBD
ps
ps
tJIT(PER,LCK) Clock-period jitter during DLL locking –100
period
tJIT.CC
Cycle-to-cycle clock-period jitter
–250
–200
+250
+200
–200
–160
+200
+160
TBD
TBD
TBD
TBD
ps
ps
tJIT(CC,LCK)
Cycle-to-cycle clock-period jitter
during DLL-locking period
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
–175
–225
–250
–250
+175
+225
+250
+250
+350
–150
–175
–200
–200
–300
+150
+175
+200
+200
+300
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
tERR(6-10PER) Cumulative error across n cycles with –350
n = 6 .. 10, inclusive
tERR(11-
Cumulative error across n cycles with –450
n = 11 .. 50, inclusive
+450
–450
+450
TBD
TBD
ps
50PER)
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
0.48
0.48
–125
0.52
0.52
+125
0.48
0.48
–100
0.52
0.52
+100
TBD
TBD
TBD
TBD
TBD
TBD
tCK.AVG
tCK.AVG
ps
Rev. 1.02, 2008-01
56
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
