Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–667
Min.
Unit
Note1)2)3)4)5)6)7)
Max.
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
ps
23)24)
8)21)
8)21)
34)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS.BASE
200
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 x tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
34)
12
25)
DQ/DQS output hold time from DQS
DQ hold skew factor
tQH
t
HP – tQHS
—
ps
26)
tQHS
tREFI
—
340
7.8
3.9
—
ps
27)28)
28)29)
30)
Average periodic refresh Interval
—
µs
—
µs
Auto-Refresh to Active/Auto-Refresh command tRFC
127.5
ns
period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1 × tCK
—
ns
31)32)
31)33)
34)
tRPRE
tRPST
tRRD
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
Active to active command period for 1KB page
size products
34)
34)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
0.35
0.4
15
—
—
0.6
—
—
—
—
ns
tWPRE
tWPST
tWR
tCK.AVG
tCK.AVG
ns
Write postamble
34)
Write recovery time
34)35)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
ns
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
34)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
RL–1
1)
V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT
.
Rev. 1.3, 2007-07
52
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
