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HYB18T1G800BC-2.5 参数 Datasheet PDF下载

HYB18T1G800BC-2.5图片预览
型号: HYB18T1G800BC-2.5
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 74 页 / 4044 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)  
1-Gbit Double-Data-Rate-Two SDRAM  
Parameter  
Symbol Note  
1)2)3)4)5)  
Self-Refresh Current  
IDD6  
6)  
CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating,  
Data bus inputs are floating.  
1)2)3)4)5)  
6)7)  
Operating Bank Interleave Read Current  
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD)  
IDD7  
,
t
RC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid commands.  
Address bus inputs are stable during deselects; Data bus is switching.  
2. Timing pattern:  
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)  
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)  
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)  
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)  
DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks)  
DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks)  
1)  
2)  
3)  
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
IDD specifications are tested after the device is properly initialized.  
DD parameter are specified with ODT disabled.  
I
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.  
5) Definitions for IDD: see Table 47  
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7.  
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT  
TABLE 47  
Definition for IDD  
Parameter  
Description  
LOW  
defined as VIN VIL(ac).MAX  
HIGH  
defined as VIN VIH(ac).MIN  
STABLE  
FLOATING  
SWITCHING  
defined as inputs are stable at a HIGH or LOW level  
defined as inputs are VREF = VDDQ / 2  
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address  
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ  
signals not including mask or strobes  
Rev. 1.3, 2007-07  
43  
03062006-ZNH8-HURV  
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