HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Timing Characteristics
Table 38
Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit Note1)2)3)4)
5)6)
Min.
Max.
+600
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–600
2
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
7)
Auto-Precharge write recovery +
precharge time
tDAL
tCK
8)
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH
275
––
––
—
ns
DQ and DM input hold time (differential
data strobe)
tDH(base)
DH1(base)
ps
ps
DQ and DM input hold time (single ended
data strobe)
t
–25
DQ and DM input pulse width (each input) tDIPW
0.35
–500
0.35
—
tCK
ps
DQS output access time from CK / CK
tDQSCK
tDQSL,H
+500
—
DQS input low (high) pulse width (write
cycle)
tCK
9)
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
—
350
+ 0.25
—
ps
Write command to 1st DQS latching
transition
tDQSS
– 0.25
150
–25
0.2
tCK
ps
DQ and DM input setup time (differential
data strobe)
tDS(base)
DQ and DM input setup time (single ended tDS1(base)
data strobe)
—
ps
DQS falling edge hold time from CK (write tDSH
cycle)
—
tCK
tCK
DQS falling edge to CK setup time (write tDSS
0.2
—
cycle)
10)11)
Four Activate Window period
Clock half period
tFAW
37.5
—
—
ns
12)12)
50
ns
13)
tHP
MIN. (tCL, tCH)
14)
Data-out high-impedance time from CK / tHZ
—
tAC.MAX
ps
CK
Address and control input hold time
tIH(base)
475
0.6
—
—
ps
Address and control input pulse width
(each input)
tIPW
tCK
Address and control input setup time
DQ low-impedance time from CK / CK
tIS(base)
350
—
ps
ps
tLZ(DQ)
2 ×
tAC.MAX
tAC.MIN
DQS low-impedance from CK / CK
tLZ(DQS)
tMRD
tAC.MIN
tAC.MAX
ps
Mode register set command cycle time
2
—
tCK
Internet Data Sheet
43
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
