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HYB18T1G800AFL-3.7 参数 Datasheet PDF下载

HYB18T1G800AFL-3.7图片预览
型号: HYB18T1G800AFL-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA68, ROHS COMPLIANT, PLASTIC, TFBGA-68]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 53 页 / 2560 K
品牌: QIMONDA [ QIMONDA AG ]
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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]  
1-Gbit DDR2 SDRAM  
Overview  
Table 2  
High Performance for DDR2–400B and DDR2–533C  
Product Type Speed Code  
Speed Grade  
–3.7  
–5  
Unit  
DDR2–533C 4–4–4  
DDR2–400B 3–3–3  
max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
266  
266  
200  
200  
200  
200  
15  
MHz  
MHz  
MHz  
ns  
min. RAS-CAS-Delay  
min. Row Precharge Time  
min. Row Active Time  
min. Row Cycle Time  
tRCD 15  
tRP 15  
tRAS 45  
tRC 60  
15  
ns  
40  
ns  
55  
ns  
1.2  
Description  
All of the control and address inputs are synchronized  
with a pair of externally supplied differential clocks.  
Inputs are latched at the cross point of differential  
clocks (CK rising and CK falling). All I/Os are  
synchronized with a single ended DQS or differential  
DQS-DQS pair in a source synchronous fashion.  
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-  
Rate-Two CMOS Synchronous DRAM device  
containing 1,073,741,824 bits and internally configured  
as an octal-bank DRAM. The 1-Gbit device is  
organized as either 32 Mbit × 4 I/O × 8 banks, 16 Mbit  
× 8 I/O × 8 banks or 8 Mbit × 16 I/O × 8 banks chip. A 17 bit address bus for ×4 and ×8 organised  
These synchronous devices achieve high speed data components and a 16 bit address bus for ×16  
transfer rates starting at 400 Mbit/sec/pin for general components is used to convey row, column and bank  
applications. See Table 3 for performance figures.  
address information in a RAS-CAS multiplexing style.  
The device is designed to comply with all DDR2 DRAM The DDR2 device operates with an 1.8 V ± 0.1 V power  
key features:  
supply. An Auto-Refresh and Self-Refresh mode is  
provided along with various power-saving power-down  
modes.  
1. Posted CAS with additive latency,  
The functionality described and the timing  
specifications included in this data sheet are for the  
DLL Enabled mode of operation.  
2. Write latency = read latency - 1,  
3. Normal and weak strength data-output driver,  
4. Off-Chip Driver (OCD) impedance adjustment  
5. On-Die Termination (ODT) function.  
The DDR2 SDRAM is available in P-TFBGA package.  
Internet Data Sheet  
4
Rev. 1.31, 2007-01  
03292006-1X3H-6X8S