Internet Data Sheet
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Chip Configuration for ×4 components, FBGA-60, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Configuration for ×8 Components, FBGA-60, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Configuration for x16 Components in FBGA–84, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 35
Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Differential Input Waveform Timing – tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Differential Input Waveform Timing – tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Outline PG-TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Outline PG-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Rev. 1.01, 2008-11
55
04212008-66HT-ZLFE
QIMONDA [ QIMONDA AG ]
