Internet Data Sheet
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 39
Absolute Jitter Value Definitions
Symbol Parameter
Min.
Max.
Unit
tCK.ABS
tCH.ABS
Clock period
t
t
CK.AVG(Min) + tJIT.PER(Min)
t
t
CK.AVG(Max) + tJIT.PER(Max)
CH.AVG(Max) x tCK.AVG(Max) +
ps
ps
Clock high-pulse width
CH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min)
tJIT.DUTY(Max)
tCL.ABS
Clock low-pulse width
tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max)
+
ps
tJIT.DUTY(Max)
Example: for DDR2-667, tCH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 40 shows clock-jitter specifications.
TABLE 40
Clock-Jitter Specifications for DDR2–667 and DDR2–800
Symbol
Parameter
DDR2–667
DDR2–800
Unit
Min.
Max.
Min.
Max.
tCK.AVG
Average clock period nominal w/o jitter
Clock-period jitter
3000
–125
–100
–250
–200
–175
–225
–250
–250
–350
–450
0.48
8000
125
100
250
200
175
225
250
250
350
450
0.52
0.52
125
2500
–100
–80
8000
100
80
ps
tJIT.PER
ps
tJIT(PER,LCK)
tJIT.CC
Clock-period jitter during DLL locking period
Cycle-to-cycle clock-period jitter
ps
–200
–160
–150
–175
–200
–200
–300
–450
0.48
200
160
150
175
200
200
300
450
0.52
0.52
100
ps
tJIT(CC,LCK)
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
tERR(6-10PER)
Cycle-to-cycle clock-period jitter during DLL-locking period
Cumulative error across 2 cycles
ps
ps
Cumulative error across 3 cycles
ps
Cumulative error across 4 cycles
ps
Cumulative error across 5 cycles
ps
Cumulative error across n cycles with n = 6 .. 10, inclusive
ps
tERR(11-50PER) Cumulative error across n cycles with n = 11 .. 50, inclusive
ps
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
tCK.AVG
tCK.AVG
ps
0.48
0.48
–125
–100
Rev. 1.01, 2008-11
49
04212008-66HT-ZLFE
QIMONDA [ QIMONDA AG ]
