Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device, containing
1,073,741,824 bits and internally configured as anoctal
quadbank DRAM. The 1-Gbit device is organized as either
32 Mbit ×4 I/O ×8 banks, 16 Mbit ×8 I/O ×8 banks or 8 Mbit
×16 I/O ×8 banks chip. These devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications.
Inputs are latched at the cross point of differential clocks (CK
rising and CK falling). All I/Os are synchronized with a single
ended DQS or differential DQS-DQS pair in a source
synchronous fashion.
A 17-bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The device is designed to comply with all DDR2 SDRAM key
features:
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
The DDR2 SDRAM is available in P(G)-TFBGA-68 and P(G)-
TFBGA-84 packages.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks.
Rev. 1.2, 2007-05
5
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
