Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
1.4
Ball Definition and Description
TABLE 4
Ball Description
Ball
Type
Detailed Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on
crossing of the positive edge of CK and negative edge of CK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides precharge power-down and self refresh
operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained
HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled
during power-down. Input buffers, excluding CKE are disabled during self refresh.
CS
Input
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code
RAS, CAS,
WE
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DQ0 - DQ31 I/O
Data Inputs/Output: Bi-directional data bus (32 bit)
DQS0, DQS1, I/O
DQS2, DQS3
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with
write data. Used to capture write data.
DQS0 corresponds to the data on DQ0 - DQ7, DQS1 to the data on DQ8 - DQ15, DQS2 to the data
on DQ16 - DQ23, DQS3 to the data on DQ24 - DQ31
DM0, DM1,
DM2, DM3
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM balls are input only, the DM loading matches the DQ and DQS loading.
DM may be driven HIGH, LOW, or floating during READs. DM0 corresponds to the data on DQ0 -
DQ7, DM1 to the data on DQ8 - DQ15, DM2 to the data on DQ16 - DQ23, DM3 to the data on DQ24
- DQ31
BA0, BA1
A0 - A12
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be
loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto
Precharge bit for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 (=AP) is sampled during a precharge command to determine whether the
PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be
precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code
during a MODE REGISTER SET command.
VDDQ
VSSQ
VDD
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity
Supply I/O Ground
Supply Power Supply: Power for the core logic and input buffers.
Supply Ground
VSS
N.C.
–
No Connect
Rev.1.00, 2007-03
7
02022006-J7N7-GYFP
QIMONDA [ QIMONDA AG ]
