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HYB18L256160BCX-7.5 参数 Datasheet PDF下载

HYB18L256160BCX-7.5图片预览
型号: HYB18L256160BCX-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用256兆移动-RAM [DRAMs for Mobile Applications 256-Mbit Mobile-RAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 48 页 / 1590 K
品牌: QIMONDA [ QIMONDA AG ]
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HY[B/E]18L256160B[C/F]X-7.5  
256-Mbit Mobile-RAM  
Functional Description  
2.4.4  
ACTIVE  
Before any READ or WRITE commands can be issued  
to a bank within the Mobile-RAM, a row in that bank  
must be “opened” (activated). This is accomplished via  
the ACTIVE command and addresses A0 - A12, BA0  
and BA1 (see Figure 9), which decode and select both  
the bank and the row to be activated. After opening a  
row (issuing an ACTIVE command), a READ or WRITE  
command may be issued to that row, subject to the tRCD  
specification. A subsequent ACTIVE command to a  
different row in the same bank can only be issued after  
the previous active row has been “closed”  
(precharged).  
#,+  
#+%  
#3  
ꢌ(IGHꢍ  
2!3  
#!3  
7%  
ꢒ $ONgT #ARE  
The minimum time interval between successive  
ACTIVE commands to the same bank is defined by tRC.  
A subsequent ACTIVE command to another bank can  
be issued while the first bank is being accessed, which  
results in a reduction of total row-access overhead. The  
minimum time interval between successive ACTIVE  
!ꢂꢎ!ꢀꢁ  
2!  
"!  
"! ꢒ "ANK ! RESS  
2! ꢒ 2OW ! RESS  
"!ꢂꢏ"!ꢀ  
Figure 9  
ACTIVE Command  
commands to different banks is defined by tRRD  
.
#,+  
!#4  
2/7  
"! X  
./0  
!#4  
./0  
./0  
2$ꢊ72  
#/,  
./0  
#OMMAN  
!ꢂꢎ!ꢀꢁ  
2/7  
"! Y  
"! Y  
"!ꢂꢏ "!ꢀ  
T22$  
T2#$  
ꢒ $ONgT #ARE  
Figure 10 Bank Activate Timings  
Table 9  
Timing Parameters for ACTIVE Command  
Symbol  
Parameter  
- 7.5  
Units  
Notes  
min.  
max.  
1)  
1)  
1)  
ACTIVE to ACTIVE command period  
ACTIVE to READ or WRITE delay  
ACTIVE bank A to ACTIVE bank B delay  
tRC  
tRCD  
tRRD  
67  
19  
15  
ns  
ns  
ns  
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:  
no. of clock cycles = specified delay / clock period; round up to next integer.  
Data Sheet  
16  
Rev. 1.11, 2007-01  
07142005-CR47-RB2E  
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