HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewFeatures
1
Overview
This chapter gives an overview of the DRAMs for Mobile Applications product family and describes its main
characteristics.
1.1
Features
The DRAMs for Mobile Applications offers the following key features:
General Features
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4 banks × 2 Mbit × 16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
4096 refresh cycles / 64 ms
Auto precharge
Commercial (0 °C to +70 °C) and extended (-25 °C to +85 °C) operating temperature range
54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
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Low supply voltages: VDD = 1.70V to 1.95V, VDDQ = 1.70V to 1.95V
Optimized self refresh (IDD6) and standby currents (IDD2/IDD3
Programmable Partial Array Self Refresh (PASR)
)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
Table 1
Performance
Part Number Speed Code
- 7.5
Unit
MHz
Speed Grade
133
5.4
6.0
7.5
9.5
Access Time (tAC.max
)
CL = 3
CL = 2
CL = 3
CL = 2
ns
ns
ns
ns
Clock Cycle Time (tCK.min
)
Table 2
Item
Memory Addressing Scheme
Addresses
BA0, BA1
A0 - A11
A0 - A8
Banks
Rows
Columns
Data Sheet
3
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
