Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Parameter
CAS latency Symbol
Limit Values
–11
Unit Note
-8
–10
–12
–14
Min Max Min. Max. Min. Max. Min. Max. Min. Max.
Delay from AREF to next
ACT/ AREF
tRFC
tXSC
52.0
—
52.0
—
52.0
—
52.0
—
52.0
—
ns
Self Refresh Exit time
1000
200
—
—
1000 —
1000 —
1000 —
1000
200
—
—
tCK
tCK
Self refresh exit followed by tXSNR
non-Read command
200
7
—
—
200
7
—
—
200
7
—
—
Power Down Exit time
tXPN
7
—
6
—
tCK
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
tATS
tATH
tKO
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
ns
ns
ns
Termination update Keep
Out timing
Rev. ID EMRS to DQ on
timing
tRIDon
tRIDoff
—
—
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
20
20
ns
ns
Rev. ID EMRS to DQ off
timing
1)
2)
3)
f
f
t
CK(min), fCK(max) for DLL on mode
CK(min) can go down to 200MHz, with tAC and tDQSCK shifted up to 1/2 tCK
HP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
4) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
5)
6)
7)
8)
t
t
t
t
MRD is defined from MRS to any other command then READ
RASmax is 8 × tREF
RCDWR(Min) may not drop below 2 × tCK
CCD is either for gapless consecutive reads or gapless consecutive writes. BL =4
9) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
10) Please round up tRTW to the next integer of tCK
11) This parameter is defined per byte
Rev. 1.3, 2007-12
34
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
