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HYB18H256321BF-11/12/14 参数 Datasheet PDF下载

HYB18H256321BF-11/12/14图片预览
型号: HYB18H256321BF-11/12/14
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆GDDR3图形内存GDDR3图形内存 [256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM]
分类和应用: 双倍数据速率
文件页数/大小: 41 页 / 2032 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18H256321BF  
256-Mbit GDDR3  
2.3  
Truth Tables  
2.3.1  
Function Truth Table for more than one Activated Bank  
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the  
chip’s multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions  
are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the  
assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD  
RTW and tWTR have to be taken always into account.  
,
t
TABLE 4  
Function Truth Table I  
Possible action in parallel on bank m  
Current State  
Ongoing action on bank n  
ACTIVE  
ACTIVATE1)  
ACT, PRE, WRITE, WRITE/A, READ, READ/A2)  
WRITE3)  
ACT, PRE, WRITE, WRITE/A, READ, READ/A4)  
WRITE/A5)  
ACT, PRE, WRITE, WRITE/A, READ6)  
READ7)  
ACT, PRE, WRITE, WRITE/A, READ, READ/A8)  
READ/A9)  
ACT, PRE, WRITE, WRITE/A, READ, READ/A 8)  
PRECHARGE10)  
ACT, PRE, WRITE, WRITE/A, READ, READ/A11)  
PRECHARGE ALL 10)  
POWER DOWN ENTRY12)  
ACTIVATE 1)  
-
-
IDLE  
ACT  
POWER DOWN ENTRY 12)  
AUTO REFRESH13)  
SELF REFRESH ENTRY 12)  
MODE REGISTER SET (MRS)14)  
EXTENDED MRS 14)  
POWER DOWN EXIT15)  
SELF REFRESH EXIT16)  
-
-
-
-
-
-
-
POWER DOWN  
SELF REFRESH  
1) Action ACTIVATE starts with issuing the command and ends after tRCD  
.
2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank is allowed  
any time. WR, WR/A, RD and RD/A are always allowed.  
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.  
4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank  
must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR is met.  
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.  
6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank  
has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR is met. RD/A is not allowed during  
an ongoing WRITE/A action.  
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.  
8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on  
another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to  
meet tRTW  
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.  
10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP  
.
.
Rev. 0.80, 2007-09  
9
09132007-07EM-7OYI